It has been fabricated on 0.18 and 2 μm FD SOI technologies and demonstrated a reduction of leakage currents by four orders of magnitude compared to standard MOS diode implementation. In particular, a new composite ULP diode is proposed and modelled. These cells take advantage of the possibility to obtain multi-threshold transistors in fully depleted (FD) SOI CMOS with no additional cost. We present new SOI basic circuit cells architectures for ultra-low power (ULP) applications that use transistors in very weak inversion. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 μm, and 0.18 μm CMOS technologies. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC < 50 ppm/☌ and ☐.35% output precision across all 25 dies. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. Prototype chips in 0.13 μm show a temperature coefficient of 16.9 ppm/☌ (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 μm2. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. This tight power budget places ultra-low power demands on all building blocks in the systems. Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. To give an example of how this vision can be used in practice, a search for all amplifier circuits was conducted that resulted in 5177 circuit topologies, some previously unknown, out of 56 862 three-transistor elementary circuit topologies. It is envisioned that the circuit topologies stored in the database can save design time and assist designers by both offering previously unknown circuit topologies and providing circuit topologies for further optimizations. This database contains 582 two-transistor and 56 280 three-transistor functional and unique elementary circuit topologies. This paper uses combinatorics to ensure that all unique circuit topologies are generated and stored in a database. In this paper, we present a method of generating all functional elementary circuit topologies. Designing analog circuits with new topologies is often very challenging, as it requires not only circuit design expertise but also an intuition of how various elementary circuits may work when put together to form a larger circuit.
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